There has been known a wafer for a semiconductor device in which an oxide film with impurities, e.g., a TEOS (Tetra Ethyl Ortho Silicate) film, a conductive film, e.g., a TiN film, a BARC (Bottom Anti-Reflection Coating) film, and a photoresist film formed by a CVD (Chemical Vapor Deposition) process or the like have been stacked in that order as a silicon substrate (see, e.g., Japanese Patent Application Publication No. 2006-190939). The photoresist film is formed to have a predetermined pattern by photolithography and serves as a mask upon etching the antireflection film and the conductive film. Besides the aforementioned wafer, another type of wafer has been also known that includes an Si-ARC (Si-containing Anti-Reflection Coating) film located between an etching target film and a photoresist film and serving as a hard mask and antireflection film.
In recent years, as semiconductor devices are manufactured smaller and smaller, there is a need of forming a more precise and minute circuit pattern on the surface of the wafer. To form a minute circuit pattern, the minimum size of a pattern in the photoresist film needs to be smaller in the process of manufacturing a semiconductor device, thus forming a small size of opening (via hole or trench) on a target film subjected to etching.
The minimum size of a pattern in the photoresist film is generally defined by the minimum size capable of being developed by photolithography and the minimum size achievable by photolithography has a limit due to, e.g., aberration in optics. For example, a minimum size attainable by photolithography is about 80 nm. Meanwhile, a processing dimension of about 30 nm is required to satisfy a need of minimizing semiconductor devices.
As the size for meeting a need of minimizing semiconductor devices is becoming smaller and smaller, it is required to develop a technology of forming an opening of such a size complying with the need on a film subjected to etching.